In the design of semiconductor integrated circuits, it is very important to consider variations in device characteristics (device mismatch) such as Vt (threshold voltage) for a given circuit design, in order to achieve circuit robustness and obtain high manufacturing functional yields for such devices.
In general, variations in device characteristics include “systematic” variations and “random” variations. Systematic variations (or process variations) are variations in a manufacturing process that equally affect some or all N-doped or P-doped elements of a local circuit depending on, e.g., the orientation, geometry and/or location of a device. For example, when manufacturing a semiconductor chip, systematic variations in device characteristics can result from variations in mask dimensions (which causes geometry variations), variations in material properties of wafers, resists, etc., variations in the manufacturing equipment and environment (e.g., lens aberrations, flow turbulence, oven temperature, etc.) and variations in process settings (implant dose, diffusion time, focus, exposure energy, etc.). Systematic variations typically have significant spatial correlations, i.e., circuits/devices that are near each other can be expected to have the same/similar amount of variations due to systematic sources of variation.
Given the high spatial correlation for systematic variations in device characteristics between local devices, body biasing methods for compensating/mitigating the sensitivity of circuit performance due to such systematic variations are well known and can be readily applied.
In contrast, random variations in device characteristics between devices of a circuit, wafer, chip or lot, are uncorrelated. Random sources of variations, which cause device mismatch between neighboring devices in a circuit, can adversely affect circuit behavior even more drastically that systematic variations in circuits such as SRAM cells and sense amplifiers. Indeed, since systematic sources of variation equally affect neighboring devices, device mismatch between neighboring devices as a result of systematic sources is negligible as compared to device mismatch due to random sources of device characteristic variation. Thus, random variations in device characteristics (device mismatch) cause significantly more deviation especially in circuit performance of the above mentioned circuits, than systematic variations. Since random variations in device characteristics are uncorrelated, methods for characterizing or modeling such random variations are difficult and inaccurate. Providing the necessary “fixes” at the device and circuit levels so as to limit the adverse effects of such random variations on circuit performance, are expansive by way of silicon area consumed as compared to those for systematic variations.
Although device mismatch may be caused by any number of variations in device characteristics, random variations in Vt (threshold voltage) mismatch have significant impact on circuit performance for various types of MOS circuits. In MOSFET devices, for example, random variations in Vt between neighboring transistors are due primarily to fluctuations in number and position of dopant atoms, but other sources include, for example, randomness in line edge roughness of devices. Variations in Vt mismatch of MOSFETs of an SRAM cell can significantly degrade cell stability as is understood by those of ordinary skill in the art. Furthermore, Vt mismatches of transistors of a sense amplifier can adversely impact the offset voltage. In particular, because a sense amplifier senses a differential voltage applied at the gates of two neighboring sensing devices (transistors), if there is a Vt mismatch between such devices, the mismatch adds to the voltage that the sense amplifier must counter before it can amplify the desired signal. By way of further example, Vt mismatches can affect the performance of CMOS inverters, e.g., a Vt mismatch can cause variations in the trip voltage, that is, the point at which the output of the inverter switches between logic states “1” and “0”.
As semiconductor integrated circuits become more highly integrated with sub-micron features sizes of MOS devices, and as power supply voltages are reduced (for low power applications), the adverse effects of circuit performance due to random variations in device mismatch are enhanced because such variations do not scale down with feature size and/or supply voltage.
Accordingly, in order to provide robust circuit designs and enhance functional yield for a given process, circuit designers will try to accurately assess/characterize the random contributions of device mismatch, such as Vt mismatch, for example, that results from a given fabrication process so as to determine the effects of such random variations on circuit performance.
Various simulations and experimental methods have been proposed and developed for characterizing variations in device characteristics to determine the effect of device mismatch in integrated circuit design. In general, such methods are based on statistical analysis or statistical modeling of device mismatches and performance differences that result from device mismatch. Statistical design methods enable a circuit designer to determine the quantitative effect of device mismatch.
For instance, CAD (computer-aided design) tools and applications have been developed for statistical circuit design and performing statistical simulations using Monte Carlo analysis. Monte Carlo simulation requires construction of a statistical model of device mismatch, for example, which model is used for simulating device mismatch. In general, with Monte Carlo analysis, parameter distributions (e.g., Normal/Guassian) are assigned to desired model parameters and then Monte Carlo simulations are performed using such parameter distributions.
There are various disadvantages associated with methods such as Monte Carlo simulations. For instance, the characterization accuracy of such methods are limited based on the accuracy of the model that is employed. Moreover, such simulations typically do not capture all the sources of Vt mismatch. Moreover, Monte Carlo simulations are expensive in terms of time and effort to develop.
Experimental techniques for characterizing device mismatch include performing statistical analysis on actual test data that is measured from test structures. For example, FIG. 1 is a diagram that illustrates a conventional test circuit and method for characterizing device mismatch. The test circuit of FIG. 1 comprises an array of NFETs or PFETs, wherein all the source terminals of the transistors in the array are commonly connected to terminal “S”. The gate terminals of the transistors in a given column of the array (10) are commonly connected to a Gi (e.g., i=1, . . . , 256) terminal, and the drain terminals of the transistors in a given row of the array (10) are commonly connected to a Di (e.g., i=1, . . . , 32) terminal. A counter and decoder circuit (11) is responsive to a clock CLK signal for generating output signals to sequentially activate one of the Gi terminals.
With the circuit of FIG. 1, test data is collected by selectively activating the transistors, one at a time, in a given sequence, to measure the drain current ID vs. gate voltage VG (I-V) characteristics for each transistor in the array (10). For example, transistor T1 in the array (10) is activated by applying Vdd to terminals G1 and D1, and then the current flowing in terminal S would be measured to obtain the I-V characteristics of T1. Then, sequential activation of the terminals Gi and Di would continue until each device in the array is measured. For instance, D1 would be maintained at Vdd while each Gi terminal would be sequentially activated under control of the counter (11) to obtain the I-V characteristics in the first row of the array (10), and this process would be repeated by sequentially activating G1-Gi for each activated row Di.
After the I-V measurements are collected for all the transistors in the array (10) and stored in a database, the data can be retrieved and processed to extract various parameters such a Vt, transconductance, drain currents, etc. and generate distributions for such parameters. In addition, the Vt of neighboring devices in the array could be compared to generate a distribution of the Vt mismatch between neighboring devices. Assuming that the transistors in the array are the same (e.g., the same channel lengths and widths), the measured distributions can be used to characterize device mismatch between the same or similar transistors to be included in a desired circuit design.
Although techniques which characterize device mismatch based on actual test data measured using test structures (such as in FIG. 1) can effectively determine parameter mismatch variance to some degree, uncertainty can be included in the test data as a result of variations from sources from other than the MOSFET being characterized, which result from the testing procedure and/or testing circuit architecture, can reduce the accuracy of device mismatch analysis. For example, in the test circuit of FIG. 1, test data that is measured for a given transistor includes uncertainty resulting from gate leakage and subthreshold leakage from unselected devices in the activated row and column.
More specifically, by way of example, when terminals G1 and D1 are activated (at Vdd) to collect data for transistor T1, the unselected transistors (T2 . . . T3) in the row D1 drive subthreshold leakage currents (current that flows from the drain to source terminal when gate voltage is below the threshold voltage), which contribute to variations in the drain current Id of transistor T1 that is being measured in terminal S. Furthermore, the unselected transistors (e.g., T4, T5) in column G1 drive gate leakage current (leakage through gate oxide from gate terminal to source terminal), which further adds to the uncertainties of the test data being measured for T1.
With the test structure of FIG. 1, other sources of variation that can add to the uncertainty include systematic (process) variations that exist when the array is too large. For instance, when the array is too large, variations in channel length of transistors in the array (10) may occur due to process variations, which contribute to parameter variations (e.g., Vt) in devices across the array (10).
Moreover, when the array is too large, the increase in temperature of the devices in the array during testing of transistors can add to the uncertainty of measured Vt, which is exponentially dependent on temperature.
Accordingly, when attempting to characterize device mismatch due to random sources, the sources of uncertainty, which result from the testing circuit and/or methodology, can contribute to the variance of the test data. As such, device mismatch due to random Vt fluctuations cannot be accurately characterized and is overestimated. This is not desirable since, as noted above, accurate characterization of random variation of device mismatch (e.g., Vt mismatch) between neighboring devices is important for circuit analysis due to the significantly adverse effects such random mismatches can have on circuit performance, functionality and yield.
Thus, it is highly desirable to develop circuits and methods that allow random Vt variations in device characteristics to be accurately and efficiently characterized for purposes of integrated circuit design.